Referring to FIG. 1, a typical data storage system comprises: an encoding subsystem 1; a decoding subsystem 2; and, a storage subsystem 3. The storage subsystem 3 comprises a storage medium such as a magnetic tape or disk, a read/write transducer for reading data from and writing data to the storage medium, and a drive system for moving the storage medium relative to the transducer. The storage medium and transducer may be alternatively implemented via optical technology. The encoding subsystem 1 transforms raw data from a user device such as a data processing system into a form compatible with the storage subsystem 3. Error correction data is typically added to the data recorded by the storage subsystem 3 during the encoding transformation. The decoding subsystem 2 transforms data read from the storage subsystem 3 back into the user data. The error correction data is employed by the decoding subsystem 2 to correct errors in the data read back by the storage subsystem 3.
Data storage systems usually have stringent reliability specifications. It is desirable to meet these specifications with cost-effective data detection and decoding. Accordingly, it is desirable to keep the implementation complexity of the decoding subsystem 2 to a minimum while maximizing performance.
Referring to FIG. 2, a typical decoding subsystem 2 for a data storage system employs a cascade of processing steps. A popular approach comprises a data detector 10 followed by an error correcting code (ECC) decoder 20. The decoder 20 may have a plurality of ECC codes.
Referring to FIG. 3, in an typical example of a decoding subsystem 2, a soft-decision based parity post processor 30 is disposed between the detector 10 and the decoder 20. A combination of data detection, inner modulation/parity codes, and outer interleaved Reed-Solomon codes is typically employed to meet the aforementioned reliability requirements.
The inner parity based coding provides performance improvement with a limited increase in implementation complexity. The data detector 10 typically employs sequence detection based on the Viterbi algorithm. The error rate at the output of the detector is improved by the post-processor 30.
In use, the post processor 30 exploits modulation and parity constraints of the inner coding. The post processor 30 receives decisions from the output of the detector 10. The post processor 30 also receives soft information from the input to the detector 10 via a feed forward link 40. The decoder 20 processes the output of the post processor using Reed Solomon codes to correct remaining errors via the outer ECC.
Errors remaining in the data after processing by the detector 10 and the post-processor 30 typically appear as bursts of various lengths. The bursts are usually broken up by the decoder 20 via multiple interleaved outer ECC code words. Various interleaving schemes are possible, depending on the length and frequency of occurrence of the bursts. Multiple levels of outer codes may be employed to further enhance the error correction capability of the system. Typically, a cyclic-redundancy-check (CRC) code is applied to detect the presence of any remaining errors in the data.
The data detection, inner decoding, and outer decoding are typically performed in a sequential, feed forward manner as shown in FIGS. 2 and 3 and generally referred to as “On The Fly” mode. In On The Fly mode, contiguous portions of recorded data are read back and processed such that decoded data is delivered at a steady data rate. This requires the detection, inner coding, and outer decoding, to be completed before the next portion of data read is processed. Thus, a careful tradeoff between performance and complexity of the detector 10 and the decoder 20 is preferable.
If the final CRC code indicates that errors remain outstanding, an elaborate “Off Line” data recovery procedure is typically initiated. This procedure is usually referred to as Off Line mode. The On The Fly mode is then interrupted, reducing the throughput of the decoding subsystem 2. The aforementioned reliability requirements necessitate exhausting all data recovery possibilities before declaring a failure. The Off Line mode may involve so-called erasure decoding of the outer codes, together with rereading and reprocessing the recorded data.
Performance improvement can be obtained by more complexity in the detector 10, post-processor 30, outer interleaved codes, and decoder 20. However, additional complexity is undesirable. Referring to FIG. 4, the performance of the detector 10 and decoder 20 may be improved by feedback 50 of the outer decoding to the detector 10 if at least one of the outer interleaved ECC code words is correctly decoded. For each correct deinterleaved outer code word, bits at corresponding positions in the interleaved data stream can be fixed or “pinned” to their correct or known values. This partially correct data stream can be reprocessed by the detector 10. Knowledge of the location and value of correct bits limits the number of possible sequences to be tracked by the detector 10 and hence improves performance. This is particularly useful for data storage systems in which the dominant noise at high recording densities is transition or media noise. In such cases, the randomness of the noise cannot be exploited by averaging many observations. Therefore, additional information relating to the correctness of specific bits in specific locations is beneficial. Use of such feedback from outer interleaved Reed-Solomon codes to inner convolutional codes is proposed for deep space applications in E. Paaske, “Improved decoding for a concatenated coding system recommended by CCSDS,” IEEE Trans. Commun., vol. COM-38, pp. 1138-1144, August 1990 and O. Collins and M. Hizlan, “Determinate state convolutional codes,” IEEE Trans. Commun., vol. 41, no. 12, p. 1785-1794, December 1993. An application of this concept to data storage is described in J. Miller and J. K. Wolf, “High code rate error correction code design for partial response systems,” IEEE Trans. Magnetics, vol. 37, no. 2, pp. 704-707, March 2001, where only an inner data detector and outer interleaved RS coding is used. An additional bit-interleaving step intersperses coded and uncoded user bits. Feedback from the corrected outer code word recovers the uncoded bits. However, the performance gain available from such a scheme is limited. Referring now to FIG. 5, another application of this concept to data storage is described in H. Sawaguchi, S. Mita, and J. K. Wolf, “A concatenated coding technique for partial response channel,” IEEE Trans. Magnetics, vol. 37, no. 2, pp. 695-703, March 2001. Here, the feed forward link 40 from the input of the detector 10 to the post processor 30 provides forward processing. ECC feedback 50 is provided from the output of the decoder 20 to the detector 10.
A conventional example of the post-processor 30 is described in R. D. Cideciyan, J. D. Coker, E. Eleftheriou, and R. L. Galbraith, “Noise predictive maximum likelihood detection combined with parity-based post-processing,” IEEE Trans. Magnetics, vol. 37, no. 2, pp. 714-720, March 2001.
An alternative approach to decoding the inner parity code involves combining the decoding and detection. Sequence detection and parity code trellises may be combined to form a joint “super-trellis”. The Viterbi algorithm may be applied to perform combined detection and decoding. However, the number of states in the super-trellis grows exponentially, and implementation complexity becomes prohibitive. For example, a detector for a degree-K generalized partial response polynomial combined with a parity code with m parity bits requires a 2^(K+m)-state trellis. A parity post-processor alleviates this problem by separating the decoding and detection.
The post processor 30 and the detector 10 operate differently. Furthermore, design of the parity post-processor 30 involves careful selection of various parameters such as the number of dominant error events to be detected, the parity code, the size of the list of most likely error events to be checked, etc.
It would be desirable to improve the performance of decoding subsystems for data storage systems.